Samsung Electronics is preparing for the introduction of its 9th Generation 3D-NAND, which employs a double-stack architecture projected for release in 2024. 

Based on information from DigiTimes that cites Seoul Economic Daily, Samsung's double-stack strategy is distinct from SK Hynix's plan to utilize a triple-stack design for their forthcoming 321-layer 3D NAND devices set for mass production in early 2025.

The double-stack technique, which Samsung previously implemented in 2020 for their 7th generation 176-layer 3D NAND chips, entails the production of a 3D NAND stack on a 300 mm wafer. This is then followed by the assembly of a second stack on the first. Such a method increases storage density per wafer, potentially making the production of SSDs more economical.

On the other hand, SK Hynix's 321-layer 3D NAND production in 2025 revolves around a triple-stack procedure. This approach involves the development of three separate 3D NAND layer sets. While it encompasses a higher number of production steps and raw material consumption, its primary objective is to enhance yields since fabricating 3D NAND stacks with fewer layers can be less complex.

Insights from industry roadmaps suggest that after their 9th Generation 3D NAND, Samsung might consider a triple-stack method for their 10th generation 430-layer 3D NAND. Analysts, cited by Seoul Economic Daily, point out that surpassing the 400-layer threshold likely requires the integration of three individual stacks, potentially due to yield considerations. This change could result in increased usage of raw materials and a rise in costs per 3D NAND wafer.

Samsung's Upcoming 300-Layer V-NAND Production and Architecture Insights