PCI Express 6.0 Specification Revision 0.3

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The PCI-SIG continues to make progress on the development of the next generation of PCIe technology – the PCIe 6.0 specification. Where you reach 16 GB/s on your PCIe Gen 3 x16 slot, that will be 128 GB/s when PCIe Gen 6 arrives.



First announced three months ago during our U.S. Developers Conference in June, the PCI-SIG members have fast-tracked development and Revision 0.3 of the specification is now complete and available to PCI-SIG member companies for review and input. PCI-SIG expects that we will be able to complete the final specification by 2021.

PCIe 6.0 technology will double the data rate to 64 GT/s while maintaining backward compatibility with all previous spec generations. Two of the key changes that are implementing include PAM-4 (Pulse Amplitude Modulation with 4 levels) encoding and low-latency Forward Error Correction (FEC) with additional mechanisms to improve bandwidth efficiency.


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PCIe VersionLine CodeTransfer Ratex1 Bandwidthx4x8x16
1.0 8b/10b 2.5 GT/s 250 MB/s 1 GB/s 2 GB/s 4 GB/s
2.0 8b/10b 5 GT/s 500 MB/s 2 GB/s 4 GB/s 8 GB/s
3.0 128b/130b 8 GT/s 984.6 MB/s 4 GB/s 8 GB/s 16 GB/s
4.0 128b/130b 16 GT/s 1.969 GB/s 8 GB/s 16 GB/s 32 GB/s
5.0 128b/130b 32 GT/s 4 GB/s 16 GB/s 32 GB/s 64 GB/s
6.0 tba 64 GT/s 8 GB/s 32GB/s 64 GB/s 128 GB/s


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