The graphics engine (GCN) architecture

The Graphics Engine Architecture

Alright, as always I keep the most complex stuff for last in the technology overview. If this seems a little too techy, then you probably want to skip this page please.

AMDs latest graphics core architecture is now marketed as GCN, which is short for Graphics Core Next architecture and the architecture building block has changed significantly to remove certain inefficiencies seen in the VLIW architecture. GCN is in its essence the basis of a GPU that performs well at both graphical and computing tasks. For the compute side of things, the GCN Compute unit model has been introduced, it is designed for better utilization, high throughput and multi tasking. E.g. performance, performance, performance. Each CU, has building block, for Hawaii it is identical towards the previous model used in the 7000 series.
 

Your basic Shader cluster is called one GCN Compute Unit, again these unites are 100% similar to the ones used in the 7000 series and feature:

• Non-VLIW Design
• 16 wide SIMD Units
• 64 KB registers / SIMD Unit

Now if we take 4 of these SIMD Units, they will form the basis of one Compute Unit (CU). 4x4=16 so each SIMD unit is 16 units wide, times four per compute unit means that each CU unit has 64 shader processors. Here we learned that one shader cluster has 64 Shader processors. So far you are with me yeah?

• AMD R9-290X has 2816 shader processors

So if one CU cluster has 64 shader processors then a 290X has 44 Compute units meaning 64SIMDs x 44 CUs = 2816 Shader processors (for the R9-290X).

• Engine has two Dual Geometry engines / Asynchronous Compute engines
• 16 render backends / 64 color ROPs per clock cycle / 256 Z/Stencil ROPs per clock
• Engine ties to 1024 KB R/W L2 cache (Upto16 64 KB L2 cache partition)
• Hawaii GPU has up-to 44 Compute Units
• 4 Geometry processors (4 primitives per clock cycle)
• 64 Pixel Output/clock

The Graphics Core Next Compute Unit (CU) has about the same floating point power per clock as the previous one (i.e. Cayman). It also has the same amount of register space (for the vector units). Each CU also has its own registers and local data share. The GCN architecture has 16-wide vector processors, again for a total of 4x16=64 operations per clock. GCN also has a scalar processor.
 

So the theoretical floating point power stays more or less the same per CU, but GCN will be more efficient since it does not require instruction level parallelism. GCN is all about creating a GPU good for both graphics and computing purposes. At the end of the pipeline, we see eight memory-controllers each 64-bit, accumulated towards a 512-bit wide bus. Combined with GDDR5 at 5.0 Gbps this will deliver the 290 series with 320 GB/sec of memory bandwidth.