Maxwell Graphics Architecture

Maxwell Graphics Architecture

Let's again put most of the data in a chart to get an idea and better overview of changes:

So we talked about the core clocks, specifications and memory partitions. However, to be able to better understand a graphics processor you simply need to break it down into small pieces. Let's first look at the raw data that most of you can understand and grasp. This bit will be about the Maxwell GM204 architecture. NVIDIA’s “Maxwell” GPU architecture implements a number of architectural enhancements designed to extract even more performance and more power efficiency per watt consumed.
 

So above, we see the GM206 block diagram that entails the Maxwell architecture, Nvidia started developing the GPU around 2011/2014 actually. Each of the two GPCs has eight SMX/SMM (streaming multi-processor) clusters in total. You'll spot the two 64-bit memory interfaces, bringing in a 128-bit path to the graphics memory at 7 Gbps, default the cards can reach 112 GB/sec.

Let's break it down into bits and pieces. The GM206 will have:

• 1024 (GTX 960) CUDA/Shader/Stream processors are used
• There are 128 CUDA cores (shader processors) per cluster
• 2.94 Billion Transistors
• 64 Texture units
• 32 ROP units
• 128-bit GDDR5 @ 112 GB/s
• Texture Filtering Rate (Bilinear) 72.1 GigaTexels/sec

One SMX: 128 single‐precision shader cores, double‐precision units, special function units (SFU), and load/store units.

• GeForce GTX 960 has 8 SMX x 8 Texture units = 64
• GeForce GTX 970 has 13 SMX x 8 Texture units = 104
• GeForce GTX 980 has 16 SMX x 8 Texture units = 128

So there's a total of up-to 8 SMX x8 TU = 64 texture filtering units available for the silicon itself (once all SMXes are enabled). Typically lower is worse, but these cards however require little voltage and can be clocked very high. And that's where performance kicks in at low power consumption. To reduce DRAM bandwidth demands, NVIDIA GPUs make use of lossless compression techniques as data is written out to memory. The bandwidth savings from this compression are realized a second time when clients such as the Texture Unit later read the data. As illustrated in the preceding figure, the compression engine has multiple layers of compression algorithms.

Any block going out to memory will first be examined to see if 4x2 pixel regions within the block are constant, in which case the data will be compressed 8:1 (i.e., from 256B to 32B of data, for 32b color). If that fails, but 2x2 pixel regions are constant, they will compress the data 4:1. These modes are effective for AA surfaces, but less so for 1xAA rendering. Therefore, starting in Fermi Nvidia also implemented support for a “delta color compression” mode. In this mode, they calculate the difference between each pixel in the block and its neighbour, and then try to pack these different values together using the minimum number of bits. For example if pixel A’s red value is 253 (8 bits) and pixel B’s red value is 250 (also 8 bits), the difference is 3, which can be represented in only 2 bits. If the block cannot be compressed in any of these modes, then the GPU will write out data uncompressed, preserving the lossless rendering requirement.

The effectiveness of delta color compression depends on the specifics of which pixel ordering is chosen for the delta color calculation. Maxwell contains the third generation of delta color compression, which improves effectiveness by offering more choices of delta calculation to the compressor. Thanks to the improvements in caching and compression in Maxwell, the GPU is able to significantly reduce the number of bytes that have to be fetched from memory per frame. Maxwell uses roughly 25% fewer bytes per frame compared to Kepler.