Alder Lake - a Hybrid Computing Architecture

Alder Lake - a Hybrid Computing Architecture

It hasn’t exactly been a secret that Intel has been putting in significant effort to re-take the CPU market. After numerous respins, it was time for a new architecture, created from the ground up with a hybrid design; meet Alder Lake, which you’ve probably already heard a lot about. They will also be the first to adopt a hybrid architecture, similar to ARM’s BIG.little, that combines high-performance cores with efficient ones, making them the first of their kind for Intel. Furthermore, this new generation is now proven to be the first to support DDR5 memory (also the DDR4) and PCI-Express 5.0, making it the first generation to do so.

Alder Lake CPU architecture has two different CPU cores

The following is a set of slides from the presentation that you can view. As previously indicated, we acquired this information hours before the embargo was lifted and will fill in the gaps throughout the day. Mind you; the Core i9-12900K has 16 cores and 24 threads. 8 P-Core (16 threads) and 8 E-Core (8 threads). The CPU has a 30 M.B. L3 cache, 3 M.B. per core (Golden Cove), and 3 M.B. per cluster (E-Core) (Gracemont). That’s 8 P-Cores for 24 MB and 6 M.B. from each of the two clusters of 4 E-Cores. The chip has 12.5 MB of L2 cache and 1.25 MB of L3 cache.

Gracemont (energy-efficient cores)

Alder Lake is Intel’s codename for the 12th-generation of Intel Core processors based on a hybrid architecture utilizing Golden Cove high-performance cores and Gracemont power-efficient cores. According to Intel, Alder Lake is a “performance hybrid” in their portfolio, focusing on performance rather than power consumption. Gracement, wasn’t that Intel Atom related? Gracemont is an upcoming microarchitecture for low-power processors that will also be used in Intel’s systems on a chip (SoCs). It will be the successor of the Tremont microarchitecture. Additionally, it will be deployed as low-power cores in a hybrid architecture for Intel’s Alder Lake processors, similar to its predecessor.  The cores have been further enhanced. Gracemont is the 4th generation out-of-order low-power Atom microarchitecture, built on the Intel 7 manufacturing process. Intel also says that Alder Lake will provide the most performance per watt of any processor. You’re going to notice several things, among them, increases in L1 caches; the Instructions cache, for example, was doubled to 64 K.B. with an up to 4 M.B. L2 cache. Remember, we’re still talking about the energy-friendly cores here. Microsoft will have to introduce these sophisticated scheduling features to x86-64 Windows to support the next-generation hardware schedulers. Key changes:

• 64 K.B. per core Level 1 instruction cache
• DDR5 memory
• PCIe 5.0 support
• Support for AVX, AVX2, and AVX-VNNI instructions

The Hybrid Architecture in Alder Lake is much different from hybrid concepts like those we are familiar with in smartphones, such as Arm’s BIG.little processor. The most important goal of various smartphone technologies in the smartphone world is to save on energy consumption. This is undeniably one of Intel’s Hybrid Architecture benefits, but the increased efficiency will also result in a higher overall perf level due to increased efficiency.

Golden Cove (performance cores)

The architecture diagrams of the low-power Gracemont cores have just been presented to you; however, Alder Lake will use its Golden Cove CPU cores when speed and performance are critical. And these should make a significant difference in IPC when it comes to processing data compared to Comet- and Rocket lake. According to Intel, Golden Cove CPU microarchitecture will take the place of the Sunny Cove, Willow Cove, and Cypress Cove microarchitectures. Originally described as 10 nm Enhanced SuperFin, it will be made using Intel’s Intel 7 manufacturing node, introduced in 2012. (10ESF). These high-performance cores will find their way into scalable processors such as Alder Lake and Xeon, as well as Sapphire Rapids. According to Intel, all of the enhancements combined should result in an improvement in IPC of 19 percent, which is on par with or slightly higher than the improvement achieved by Sunny Cove when compared to Skylake. That should even be sufficient to dethrone the Zen 3 architecture of the Ryzen 5000 CPUs.

According to Intel, Alder Lake-S will include 8 Golden Cove cores and 8 Gracemont cores, who verified this during the company’s architecture day. It will be manufactured utilizing Intel’s Intel 7 technology, previously known as the Intel 10 nm Enhanced SuperFin process. As previously stated, Alder Lake-S will have 8 Golden Cove cores, high-performance cores, and 8 Gracemont cores, which are high-efficiency cores. Because Gracemont cores do not support Hyper-Threading (H.T.), Alder Lake-S will only provide 16 cores and 24 threads, the same as the i9-12900K configuration.

CPU

• Further information: Golden Cove (microarchitecture) and Gracemont (microarchitecture)
• Golden Cove high-performance CPU cores
• New instruction set extensions[6]
• Gracemont high-efficiency CPU cores
• Next-generation hardware scheduler; adding support for these advanced scheduling capabilities will require Microsoft to add them to x86-64 Windows.

GPU

• Intel Xe (Gen12.2) GPU

I/O

• New LGA 1700 socket[8]
• PCI Express 5.0
• DDR5 memory support for desktop CPUs
• LPDDR5 memory support for laptop CPUs
• DMI 4.0 x8 link with Intel 600 series PCH chipsets 

According to the manufacturer, the integrated graphics are based on Xe, and it has up to 96 E.U.s for the GPU and 32 E.U.s for media functions only. For a fully equipped processor, you’ll receive eight performance cores as well as eight energy-efficient cores; the performance cores have SMT (hyper-threading), which means you’ll end up with a total of 24 CPU threads. 

DDR5 Memory subsystem

The memory subsystem, DDR4, and DRR5 compatible have a large amount of transistor real estate Intel invested heavily in. Intel continues to list memory at the JEDEC specification level, implying that it cannot go further. DDR4 memory operates at 3200 MHz, while DDR5 memory operates at 4800 MHz by default. You can already see that the memory bandwidth is likely to rise dramatically with DDR5 technology. So support at JEDEC defaults is Dual Channel PC5-38400U (DDR5-4800) or PC4-25600U (DDR4-3200). New and included in DDR5 is XMP 3.0, in total 5, but up to three manufacturer timing and frequency profiles can now be stored inside the DIMM. However, two remaining profiles can be configured and written by the end-user. If you can find a sweet spot for your memory (frequency, timings, and voltage-wise), you can store that profile to SPD. 

PCI Express 5.0

Alder Lake will enable PCI Express 5.0, which will more than double the bandwidth available from Gen 4, reaching a whopping 64 GB/s over 16 lanes, as predicted by rumors and now confirmed by Intel. Comparatively, PCIe Gen 3.0 (fast) can carry 16 GB/s across 16 lanes. Interconnects will be required to connect everything. AMD refers to this as the infinity fabric, whereas Intel refers to it as the compute fabric, two distinct names for the same concept. The DMI interface between CPU and chipset also has received a massive upgrade to DMI 4.0, 16GT/s (PCIe 4.0 x8).

The Z690 chipset

Intriguing is the diagram for the Z690 chipset, which is the highest-end model released first. What was previously said appears correct; the chipset has 12 times gen4 and 16 times gen3 processors. The CPU has 16 (or two times 8 PCIe 5.0 lanes), which can be used for graphics or storage, in addition to four NVME 4.0 lanes. Additional features include support for two DIMMs per memory channel and dual-channel DDR4-3200 or DDR5-4800 with two DIMMs per memory channel.

• Supports both DDR4 and DDR5, with standard data rates of at least DDR5-4800 compliant on four-module configurations.
• Will automatically use Gear 2 or Gear 4 modes for DDR5, running the memory controller at ½ or ¼ speed, depending on data rate.
• Retains 20 CPU PCIe lanes, but 16 are increased to PCIe 5.0 data rates.
• Uses DMI 4.0 to connect the CPU to the PCH (chipset) at PCIe 4.0 x8 speeds.
• New PCH has four more PCIe lanes, including 12 PCIe 4.0 and 16 PCIe 3.0.
• Supports up to four USB 3.2 2×2 (20Gb/s) ports.
• New CNVio modules support Intel Wi-Fi 6E and possibly Wi-Fi 7.
• Uses “Big-Bigger” hybrid cores to improve thread handling while retaining 125W TDP.
• Lower stack height requires a new CPU cooler bracket.

To improve the performance, the Direct Media Interface link is being upgraded from DMI 3.0 x8 to PCIe 4.0. There are 5 and 1 gigabit Ethernet, four USB 3.2 gen 2x2 ports, and Wi-Fi 6E standards.