baasgene:

Intel, please get rid of your in house chip maker and just contract these guys please.

sbacchetta:

Impossible, Intel needs in wafer quantity is too big, even if Intel were the sole customer of TSMC, it would probably still not be enough... Edit: TSMC supply would be sufficient, but Intel would need more than a third of it -> not gonna happen.

Ssateneth:

Also, what the node is named as is mostly becoming marketing terms these days. Transistor density would be a better representation of how much something shrinks.

Compared to it’s N5 node, N3 promises to improve performance by 10-15% at the same power levels, or reduce power by 25-30% at the same transistor speeds. Furthermore, TSMC promises a logic area density improvement of 1.7x, meaning that we’ll see a 0.58x scaling factor between N5 and N3 logic. This aggressive shrink doesn’t directly translate to all structures, as SRAM density is disclosed at only getting a 20% improvement which would mean a 0.8x scaling factor, and analog structures scaling even worse at 1.1x the density. Modern chip designs are very SRAM-heavy with a rule-of-thumb ratio of 70/30 SRAM to logic ratio, so on a chip level the expected die shrink would only be ~26% or less.