That graph is strange... how does moving from 14nm to 10nn more than double the transistor density(40mio/mm² @ 14nm -> 100mio/mm² @ 10nm = -28% size, 2.5x density)? Especially if the previous larger shrinks only allowed for a smaller improvement (18mio/mm² @ 22nm -> 40mio/mm² @ 14nm = -36% size, 2.22x density)

Also recall when Intel moved to using FinFets back when they were at 22nm ie "transistors in the 3d dimension" they called it. People gloss over this all the time but now chips are 3d the nanometers taken from the smallest feature the lithography can make really doesn't mean much anymore. It meant a lot more back when chips were "2d" since it directly contributed to the gate length which had a fairly predictable shrink but it was mostly marketing then too. So the little fins that stick up like a microscopic sharks fin contribute a lot to density as well. Instead of just measuring width you now have to account for the length and the pitch or what angle the pieces lean over on the 3d pieces. I tried to keep this rather high level on purpose. The short of it is lithography feature size doesn't translate to densities anymore since chips are now in 3d.