AMD Zen 4 Die Cache Sizes, Latencies And Transistor Counts Detailed
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Horus-Anhur
Strange that the L3 cache latency increased.
For the L2 is expected, as it doubled the size. But L3 is the same.
Could it have been adjusted for higher clock speeds of the Zen4?
JamesSneed
That is what it is per the guy who posted this aka Retired Engineer. They have the L3 cache running at much higher frequencies, so I expect real world testing to show the actual latencies are about the same.
Picolete
Is the I/O chip still also used as a chipset? I hope this new boards don't need active cooling on the chipset
GlassGR
i wonder what was the deference of L2 cache latencies between i7 2600k and i7 3770k !
ah i see there were no competition back then so no one gave a sh**.
Kaarme
Considering the IO chip includes an iGPU, I hope not.
user1
given that they are pushing for 5.7ghz doesnt surprise me, unlike modern intel chips the cache frequency is locked with the cores on amd (dont think this has changed for zen4). reminds me of somethig i read a while back in the core 2 days, the legendary e0 stepping of the 45nm chips supposedly has looser cache timings and this allows those chips to hit ~4.5ghz+ where as the older c0 stepping gets stuck around 4.0-4.2ghz, but offers very slightly higher ipc.
umeng2002
There is no way they would enable the iGPU if an I/O die was used as a Southbridge.
JamesSneed
No its not this gen but I wouldn't doubt that comes in the future. AMD has said there will be no need for active cooling this generation.
