Memory timings – a bit of theory

Memory timings – a bit of theory

The overall rule is simple – the lower the number, the better it is for the performance. When you look at the specs of a memory kit, for example the reviewed memory kit, you will see something like: CL16-18-18-36 1.35V (2T). What does it mean? Well, this refers to CAS-TRCD-TRP-TRAS, and CMD. These values are measured in clock cycles.

• CAS latency (CL) – the number of cycles between sending a column address to the memory and the beginning of the data in response. This is the number of cycles it takes to read the first bit of memory from a DRAM with the correct row already open. Unlike the other numbers, this is not a maximum, but an exact number that must agree between the memory controller and the memory.
• Row Address to Column Address Delay (TRCD) – it’s the minimum number of clock cycles required between opening a row of memory and accessing columns within it. The time to read the first bit of memory from a DRAM without an active row is TRCD + CL.
• Row Precharge Time (TRP) - the minimum number of clock cycles required between issuing the precharge command and opening the next row. The time to read the first bit of memory from a DRAM with the wrong row open is TRP + TRCD + CL.
• Row Active Time (TRAS) - the minimum number of clock cycles required between a row active command and issuing the precharge command. This is the time needed to internally refresh the row, and overlaps with TRCD. In SDRAM modules, it is simply TRCD + CL. Otherwise, approximately equal to TRCD + 2×CL.
• Command Rate (CR) - Now, 1T means it takes 1 clock cycle to "find" a memory bank, vs. 2T where it takes 2 clock cycles to "find" the memory bank. Whether the chip select can be executed in a single clock or whether it needs two clocks, depends on a variety of factors. Among the most crucial contributing factors appears to be the number of banks populated within the system from which the correct bank has to be selected. In a single bank configuration, the system already knows that all data have to be within this bank. If more banks are populated, there is an additional decision involved.

Testing the optimum timings can be very time-consuming, and it’s a matter of many attempts to achieve stability. Fine tuning the above settings can definitely bring some really nice improvements (especially Command Rate is commonly underestimated). There are some further timings, which most users leave for the motherboard to configure automatically, but they can be useful when you’re joining the competition to beat some world records in SuperPi (but I’m not, so I always skip that part).